Single Chip 3.5GHz Doherty GaN  PA for sub-6GHz 5G


This fully integrated 3.5GHz Doherty PA MMIC was realised on the 0.4µm gate length GaN-on-SiC process from GCS. It was housed in a custom laminate SMT package fabricated and assembled in the UK by Filtronic .

The die measures 4.0 by 4.7mm and is packaged in an 8×8 mm custom laminate QFN package. The 0.4µm GCS process operates at a drain voltage of 28V, enabling high output powers and reducing current losses. A symmetrical Doherty topology was selected to simplify the design procedure and reduce development times. The main and auxiliary stages have individual driver stages for higher PAE in back-off and to allow flexibility in the biasing arrangement. The PAE measured at 3.5GHz under large-signal pulsed conditions is plotted below. The MMIC was measured in both ‘Doherty’ mode (with the auxiliary amplifier biased in Class C) and in ‘balanced’ mode (with the auxiliary amplifier at the same bias current as the main amplifier). The plot below clearly shows the superior back-off efficiency of the Doherty mode of operation.



Using a 5G NR signal with 11.5dB PAPR, the linearity of the PA was measured. Good linearity performance was measured without the use of analogue predistortion (APD) or digital predistortion (DPD) and these techniques could be used to further improve the linearity. The EVM plot shows that, with the selection of an appropriate gate bias voltage, the Doherty mode of operation is capable of better performance than the balanced mode whilst also exhibiting better back-off efficiency.



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